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enjoy-digital
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liteiclink
Small footprint and configurable Inter-Chip communication cores
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SERDES bench file for LiteX Acron baseboard
#21
ohault
opened
2 months ago
0
New URL for ARTIQ
#20
ohault
opened
2 months ago
0
Compatibility with Zynq7000 FPGAs
#19
JoyBed
closed
3 months ago
2
GTPQuadPLL: refclk is connected to GTREFCLK0 by default
#18
hansfbaier
closed
3 months ago
1
GTPQuadPLL: refclk is connected to GTREFCLK0 by default
#17
hansfbaier
closed
3 months ago
2
serwb/efinix: name rx_sys clkout
#16
rtucker85
closed
7 months ago
1
[Feature request] adding support of Universal Chiplet Interconnect Express (UCIe)
#15
ohault
opened
1 year ago
0
serwb: Fix shifting
#14
cklarhorst
closed
1 year ago
1
WIP: Serwb improvements
#13
cklarhorst
opened
1 year ago
3
genphy: Fix init _SerdesClocking for diff clks
#12
cklarhorst
closed
1 year ago
1
add manifest, uplift setup.py to pass twine checks
#11
timkpaine
closed
1 year ago
1
bench: add ecpix5 serdes config
#10
sergachev
closed
2 years ago
1
Fix python3.6 more than 255 arguments to a function.
#9
cbalint13
closed
2 years ago
1
UltraScale GTH support
#8
smunaut
closed
2 years ago
1
serdes_ecp5: fix rx_los connection, fix a comment; versa_ecp5: fix a counter
#7
sergachev
closed
2 years ago
1
test_prbs: Handle PRBS error counter wrap around
#6
smunaut
closed
2 years ago
1
GTHE3: Verify QPLL operation on KCU105.
#5
enjoy-digital
closed
1 year ago
3
Build for versa_ecp5.py serdes sample fails
#4
goran-mahovlic
closed
2 years ago
4
[question] Loopback test with serwb
#3
kamejoko80
opened
3 years ago
9
Nexys SerWB example not building
#2
rlipperts
closed
3 years ago
4
Feedback / Contribution / Support
#1
enjoy-digital
opened
4 years ago
0