Problems with inter clock timing

[cklarhorst]

Hi all,

I'm trying to get litepcie to work on a custom board with a kintex. While looking at the vivado output, I noticed many inter clock paths failing. I also tried the sqrl_acorn board and it also has the same failing paths:

Example vivado timing log from sqrl_acorn with pcie enabled:

------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock         To Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints
----------         --------               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------
s7pciephy_clkout0  sys_clk                 -5.005      -42.734                      9                    9        1.892        0.000                      0                    9
s7pciephy_clkout1  sys_clk                 -4.998      -42.669                      9                    9        1.899        0.000                      0                    9
s7pciephy_clkout3  sys_clk                 -6.265    -1978.372                    366                  366        1.767        0.000                      0                  366
s7pciephy_clkout1  s7pciephy_clkout0        0.029        0.000                      0                 2489        0.053        0.000                      0                 2489
s7pciephy_clkout0  s7pciephy_clkout1       -0.359       -0.359                      1                 2488        0.053        0.000                      0                 2488
sys_clk            s7pciephy_clkout3       -3.638      -23.324                     13                   13        0.611        0.000                      0                   13

I discovered that https://github.com/enjoy-digital/litex/blob/0c326f0ed009ce6cf8b000bb4b6c67ff595a766e/litex/soc/integration/soc.py#L2024 sets everything between sys_clk and pcie to a false path. But I'm not sure what the pcie clock domain is and if that is maybe the source of my problem. In https://github.com/enjoy-digital/litepcie/blob/a20bf8827793bf2aca69f131b4da2f6f212c4f43/litepcie/phy/s7pciephy.py#L230 pcie clock domain is only about the axi output clk. Does anybody know how that is supposed to work, should all paths between the clocks in litepci and sys_clk be set to false paths? In my opinion, the false path should be set between the pcie ref input clock (for sqrl_acorn that would be pcie_x4_clk_p) and sys_clock so that all clocks generated inside litepcie are also considered false paths instead of now where the false path is between "pcie" (The axi output clk inside litepcie) and "sys_clk".

The current version doesn't even set the false path. Vivado prints: CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -include_generated_clocks -of [get_nets pcie_clk]]'

Relevant lines from the generated XDC file:

create_clock -name pcie_x4_clk_p -period 10.0 [get_ports pcie_x4_clk_p]
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets pcie_clk]] -asynchronous

Maybe I'm totally on this. Thanks in advance for any hints on this.