Open vbuitvydas opened 1 year ago
@vbuitvydas: Sorry for the delay, this is a configuration that is used by some users/clients. It could be worth testing with updated LiteX and provide us the exact steps/files to reproduce the issue. Have you also tested an approach similar to the integration done for the LitePCIe's bench or LiteX-Boards' targets? If working, this would indicate an issue with the litepcie_gen
approach that we could try to understand/fix together.
I am unable to run dma_test with external loopback option from litepcie_util: ./litepcie_util dma_test -w 32 -e litepcie_util prints that 129 TX buffers are sent and zero RX buffers received but no data received at FPGA side and dma0_reader_axi_tvalid never gets asserted.
Other tests seems to be working, I have tried dma_test with internal loopback and it is working: ./litepcie_util dma_test -w 32
I am using: litepcie sha - c332352c0b2b9167b68e560635c3f5ed54b3d8c1 Dev board - Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit
I have generated litepcie based on ac701.yml example and made these changes: “phy”: “USPPCIEPHY” “phy_device”: “xczu7ev”
On FPGA side I have connected AXIS data FIFO between dma0_reader and dma_writer ports to have external loopback.
Is there any options or modifications that I am missing? Thanks in advance for any help.