Cleanup Xilinx US/USP PHY integration. - Githubissues

enjoy-digital / litepcie

Small footprint and configurable PCIe core

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Cleanup Xilinx US/USP PHY integration. #123

Closed enjoy-digital closed 10 months ago

enjoy-digital commented 11 months ago

Switch to .tcl for PHY generation (similar to 7-Series).
Move AXI/TLP adaptation logic outside of pcie_support.v.
Remove .xci files and duplicated code.