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enjoy-digital / litepcie

Small footprint and configurable PCIe core
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A LitePCIeDMA class question #51

Closed jimmymagemtek closed 2 years ago

jimmymagemtek commented 2 years ago

Hi Sir, By https://github.com/enjoy-digital/litex/issues/983,

I realize that the Host is just advertised by separate DMAReader/DMAWriter IRQs of the progress/status on the FPGA.

Then, how does the host ensure that writes are done ahead of FPGA reads (DMA Reader, Host --> FPGA) and reads are done after FPGA writes (DMAWriter, FPGA --> Host) ?

Since the host seems to have no way to let FPGA to follow its write or wait for its read.

Please advise. Many thanks. Jimmy

enjoy-digital commented 2 years ago

Hi @jimmymagemtek,

In LitePCIe, the FPGA is the one maintaining the Scatter-Gather loop indexes and regulating the transfers. The Host is just advertised by separate DMAReader/DMAWriter IRQs of the progress/status on the FPGA and has to ensure that writes are done ahead of FPGA reads (DMA Reader, Host --> FPGA) and reads are done after FPGA writes (DMAWriter, FPGA --> Host).

enjoy-digital commented 2 years ago

Closing since question has been answered. @jimmymagemtek since you are using a custom design built for a partner, can you contact the partner if you need more support than the one I can provide here?