Closed sergachev closed 2 years ago
Thanks! This looks good. I'll have a closer look and also do integration tests on some projects. For Ultrascale(+) we'll have to do https://github.com/enjoy-digital/litepcie/issues/42 first (or at least move the adaptation code).
I've tested this locally on x1, fairwaves xtrx, and it tests fine. This seems quite simpler for configuring the IP!
Thanks @sergachev, I've been able to also test it and verify that it does not break other designs where I'll keep specific pre-generated verilog files.
We can switch from huge auto-generated xci files to minimal IP instantiation with Tcl directly in our code using only the required parameters.
I only tested X1 compilation and on hardware.
Most likely even more parameters in the
config
dict can be removed / auto-calculated.