Closed smunaut closed 2 years ago
So I tried tracing the various state it goes through during several events :
Initial configuration ( with PC already booted )
Trigger retrain ( set retrain bit on the root port bridge )
Disable link : ( set disable link bit on the root port bridge )
Enable link : ( clear disable link bit on the root port bridge )
Reboot
This can end up in one of two scenarios :
or :
In both cases, I can't get it to change state ever again, no matter what bits I try to poke on the root bridge (setting it to sleep, disabling/re-enabling link, request retrain, ...)
Other interesting result is I tried commenting out https://github.com/enjoy-digital/litepcie/blob/master/litepcie/phy/usppciephy.py#L97
Idea is that I can imagine some of the logic wants to see a clock when reset is asserted.
And that seems to reliably allows the FPGA to be detected through a reboot !
It's not all perfect though, because when I do that, it seems I can no longer dynamically reload a bitstream when the machine is booted :/ The PCIe core then follow that sequence during a "dynamic" reload :
And I can't get it out of it. (even manually asserting the pcie_rst_n on the core just makes it go through the same sequence). If I reboot the machine, it will train and work just fine though.
This might be something to do with the bios programming something differently when the card is detected at boot and when it's not that prevents a dynamic reload.
Closing as I don't think the remaining weirdness is LitePCIe related and the removal of the clock gating on reset fixed most of them.
Issue
Trying to bring up PCIe (gen3 4x and gen3 8x) on this board yielded some unexpected issues and it took some time to find a sequence that works.
I'm documenting here the observations, the theory about what I think the problems are and workarounds.
Test Setup
First description of the setup :
Initial Observation ( Feb 22 )
Card plugged in mobo PCIe1 (16x)
Card plugged in mobo PCIe3 (1x) via a 'usb cable extender'
Card plugged in an external PCIe switch, the PCIe switch connected to mobo PCIe3
Card plugged in an external PCIe switch, the PCIe switch connected to mobo PCIe1
Card plugged in mobo PCIe1 (16x) via a 'usb cable extender' (limiting to 1x)
Theories about problems ( Feb 23 )
Following more testing the next day, I think there are several problems and that's why the symptoms are weird and the different cases results make little sense.
If the card isn't detected at boot, the bios seems to not bother to configure the PCIe root port. So I have to manually write the LinkControl register in linux to set it up properly to get gen3 support and get it to train properly.
When doing a pcie rescan, even if it detects the device ... linux is dumb as a brick and will not configure the memory zone through the upstream switches/root ports, they remain [disabled]. Solution for that is to do a delete of the pcie root port where the card is plugged, and then do a rescan. When linux will re-add the bridge, it will then properly configure it for the downstream devices.
For some reason, once the PCIe core has trained once ... it cannot go through a reboot cycle, that will lock it up. So if I configure it before the machine is started, then boot, it's fine. Or if I boot with the card unconfigured and do it all once in linux, that works too. But if I get the card up and try a warm boot, it will never be seen ever again.