Closed ShawnLess closed 6 years ago
You can try to use toolchain_path="your_toolchain_path" here: https://github.com/enjoy-digital/litepcie/blob/master/example_designs/make.py#L154
Note that if you want to build this example design, you will need to have a valid license for a xc7k325t. I should add an example design for artix7 too.
Hi :
Thanks for the kind reminder. I will check if we have that license feature.
Anywhere, is it possible to generated RTL only? we don’t need bitstream at this stage.
Regards, Shaolin.
On 1 Feb 2018, at 12:02 PM, enjoy-digital notifications@github.com wrote:
Note that if you want to build this example design, you will need to have a valid license for a xc7k325t. I should add an example design for artix7 too.
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Adding toolchain_path="your_toolchain_path" to: https://github.com/enjoy-digital/litepcie/blob/master/example_designs/make.py#L154 worked perfectly.
Anywhere, I lack the license to generate the bitstream.
Closing since solved.
Hey guys: Nice work but I still ran into problem after I installed the Xilinx tools:
I installed the vivado in a dir other than /opt/Xilinx/Vivado. How can I change that? I there any parameter that I can override on command line?
Thanks in advance.