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enjoy-digital / litepcie

Small footprint and configurable PCIe core
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phy: Add optional LTSSMDebug module #91

Closed smunaut closed 2 years ago

smunaut commented 2 years ago

This records every state that the LTSSM state reported by the PHY goes through and pushes it to a FIFO that's readable via the CSR interface.

A small python script that reads and decodes that FIFO is also included (through UARTBone/JTAGBone or such. NOT the PCIe bridge !)

Signed-off-by: Sylvain Munaut tnt@246tNt.com

enjoy-digital commented 2 years ago

Great, thanks @smunaut, this will be very useful to diagnose PCIe bring-up issues.

enjoy-digital commented 2 years ago

@smunaut: I just did some minor integration changes with https://github.com/enjoy-digital/litepcie/commit/01e8b57f471f995a8dcc74f13e64db0fc0c87bdb.