DMA tlast and tkeep missing

[1n3o1]

Thanks in advance for you effort . unfortunately there is no connection form pcie endpoint DMA to user area for tlast of packets and also tkeep If I wanted to use 128 bit width data then there is chance that I read 5 64bit then the last one will be transfred in in 128 bit width field but its tkeep will be zero (regrading to xilinx pcie endpoint doc ). as you know pcie transfer with the word width of 32bit (if i am not wrong) but xilinx endpoint in 128bit mode has to output 128 bit for that matter it uses tkeep to indicate the unregistered data . but in your IP tkeep and tlast has been drop from TLP handler to DMA and there is no tkeep after dma and also no tlast

[enjoy-digital]

LitePCIe is using LiteX's stream internally and indeed expects the user to use full-word transfers (ie with descriptors' length multiple of PCIe Bus data-width). Supporting partial-word transfers would probably be possible but is not currently implemented.

If you want to help implementing this or fund this work, please get in touch.