Arty fast scope

[keesj]

I have been doing some work on faster sampling. Because my signals are faster than the system clock I am using a serdes on the arty board. As a result the analyzer dumps of my bitstream needed to be flattened again. With that done I can analyze the dumps on a logic anlayzer (sigrok)

The only way (without changing to much) was to flatten the data before dumping it hence these changes.

Suggestion to remove some duplication (or locations of the files are welcome)

The image bellow shows my sampling a 200 MHz signal generated on a tinyfpga-bx

//icepll -i 16 -o 200 -m -f h

SB_PLL40_CORE #(
        .FEEDBACK_PATH("SIMPLE"),
        .DIVR(4'b0000),     // DIVR =  0
        .DIVF(7'b0110001),  // DIVF = 49
        .DIVQ(3'b010),      // DIVQ =  2
        .FILTER_RANGE(3'b001)   // FILTER_RANGE = 1
    ) uut (
        .LOCK(locked),
        .RESETB(1'b1),
        .BYPASS(1'b0),
        .REFERENCECLK(CLK),
        .PLLOUTCORE(clk_200mhz)
        );

  // 4 bits counter with 0 as initial value
  reg [30:0] counter;
  initial counter = 5'b0;

  initial USBPU = 0;

  assign PIN_1 = clk_200mhz;
  assign PIN_2 = ~clk_200mhz;
  assign PIN_3 =counter[0];
  assign PIN_4 =~counter[0];

[enjoy-digital]

Thanks, that's a nice example. I'll try to test it/merge it next week.

[enjoy-digital]

Thanks, it's merged. I'll maybe do some change on it (i'll indicate the changes here when i'll do it). I'm also wondering about creating a kind of litex-playground repository for similar examples, if we create it, we'll maybe move it there.

[keesj]

Thanks, it's merged. I'll maybe do some change on it (i'll indicate the changes here when i'll do it). I'm also wondering about creating a kind of litex-playground repository for similar examples, if we create it, we'll maybe move it there.

The problem I had what that I needed changes in the dump module.