software/dump/sigrok: Support width > 1.

enjoy-digital / litescope

Small footprint and configurable embedded FPGA logic analyzer

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Closed zyp closed 4 years ago

zyp commented 4 years ago

Enable dumping variables with width > 1 by splitting them into one probe per bit.

zyp commented 4 years ago

Pushed an update to fix the test I broke. The remaining test failure appears to be unrelated and caused by changes in litex.

enjoy-digital commented 4 years ago

Thanks! That's merged. The test failure has been fixed.