search

enjoy-digital / litescope

Small footprint and configurable embedded FPGA logic analyzer
Other
160 stars 38 forks source link

Is it possible to debug the litedram phy with litescope? #23

Closed cklarhorst closed 3 years ago

cklarhorst commented 3 years ago

I'm currently trying to bring litex to a custom spartan6 board with LPDRAM (using S6HalfRateDDRPHY). I'm able to analyze the dfi but is it possible to capture signals more near the PHY pads (e.g including things like bitslip or the dqs pattern)? I tried analyzer_signals = [self.ddrphy] in hope to see as much as possible but it results in TypeError: object of type 'S6HalfRateDDRPHY' has no len(). analyzer_signals = [platform.lookup_request("ddram")] also doesn't work:

ERROR:NgdBuild:924 - bidirect pad net 'ddram_dq<0>' is driving non-buffer
   primitives:
     pin I1 on block
   trigger_sink_sink_payload_data[232]_trigger_mem_source_payload_mask[232]_and_
   521_OUT<212>1 with type LUT3,
enjoy-digital commented 3 years ago

@cklarhorst: first, i'm not sure you are aware of that, but there is a page in the LiteX's Wiki explaining how to use LiteScope. This could still be improved, but at least give a way to start: https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC

With LiteScope, you'll be able to observe all signals of the FPGA fabric, but when hardware primitives are used, it's possible you'll be limited by what is physically possible. If there are no direct route going to the fabric, then it's not possible to visualize it with LiteScope. It's possible LiteX will allow you to generate the design since not aware of the hardware limitations, but it will then fail when building the design with the toolchain.

On the S6HalfRateDDRPHY, you won't be able to visualize the signals at the IOs level, because with the primitives used, it's not possible to route these signals to the Fabric, but you'll be able to visualize the signals at the DFI level and the logic inside the PHY. Since Migen/LiteX are python based, to add a signal inside submodules, you can just do:

analyzer_signals = [
    self.module1.module11.module111.signal1,
    self.module1.module11.module111.signal2,
    self.module1.module11.module112.signal1,
   etc...
]

You can find a more complete example here: https://github.com/enjoy-digital/usb3_pipe/blob/master/netv2.py#L101-L13

enjoy-digital commented 3 years ago

The question has been answered and we can probably close this.