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enjoy-digital / litescope

Small footprint and configurable embedded FPGA logic analyzer
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Fix: 2 signals in the storage class belong to the wrong clock domain #27

Closed cklarhorst closed 4 years ago

cklarhorst commented 4 years ago

Signals & Domain overview:

Therefore, everything that involves mem needs to use offset/length

enjoy-digital commented 4 years ago

Thanks for catching this!