dump.vcd is empty when debugging via PCIe interface

enjoy-digital / litescope

Small footprint and configurable embedded FPGA logic analyzer

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dump.vcd is empty when debugging via PCIe interface #33

Closed jimmymagemtek closed 2 years ago

jimmymagemtek commented 3 years ago

Hi Sir, I am able to dump register values inside FPGA using "litex_client.py --regs", so I supposed litex_server.py is working properly via PCIe interface with FPGA (My board is a PCIe card with FPGA on it).

But when I use "litescope_cli.py --csv=filename.csv -r signalname", I get "dump.vcd while it is empty(size is around 130k). I open it with gtkwave & see no waveform.

Do you have any idea why "litescope_cli.py" always get empty dump.vcd ? Please advise. Thanks.

Jimmy

enjoy-digital commented 2 years ago

Hi @jimmymagemtek,

as discussed in other issues, you are probably using a design from a partner and things are probably different than in LiteX-Boards targets so it's difficult to do support here. Please get in touch with me or the partner to find a way to provide you support.