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enjoy-digital / litescope

Small footprint and configurable embedded FPGA logic analyzer
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core: Change upload protocol to allow bursting through xBone #41

Closed smunaut closed 2 years ago

smunaut commented 2 years ago

Instead of using a very wide CSR, we force it to max 32 bits and read each captured words as several sub-words.

Also, instead of checking for 'valid' flag every time, we just read the 'level' of the memory buffer. Given the way LiteScope works, we know capture is done and this is how many words there is to read.

All in all this means that reading the data off the buffer is just reading the same address over and over meaning we can use very long bursts which helps _alot to speed things up.

Signed-off-by: Sylvain Munaut tnt@246tNt.com

enjoy-digital commented 2 years ago

Thanks @smunaut! The code changes make sense and I've been using it the last fews days in different configurations over JTAGBone and Etherbone without troubles so we can merge.

enjoy-digital commented 2 years ago

@smunaut: I just did a minor change with https://github.com/enjoy-digital/litescope/commit/13813457d74152e8c21f899508636ca374897500 to simplify the code and fix the case where pad_bits == 0.