SDROutput and nextpnr+xilink platform

[suarezvictor]

When using nextpnr+xilinx, ODDR instances for VideoGenericPHY keeps being generated even when SDROutput is requested

a temporary solution found was to replace the SDROutput with direct assignment (in https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/video.py#L700)

class VideoGenericPHY_SDR(Module):
    def __init__(self, pads, clock_domain="sys"):
        self.sink = sink = stream.Endpoint(video_data_layout)

        # # #

        # Always ack Sink, no backpressure.
        self.comb += sink.ready.eq(1)

        # Drive Clk.
        if hasattr(pads, "clk"):
            self.comb += pads.clk.eq(ClockSignal(clock_domain))

        # Drive Controls.
        if hasattr(pads, "de"):
            self.comb += pads.de.eq(sink.de)

        if hasattr(pads, "hsync_n"):
            self.comb += pads.hsync.eq(~sink.hsync)
        else:
            self.comb += pads.hsync.eq(sink.hsync)

        if hasattr(pads, "vsync_n"):
            self.comb += pads.vsync.eq(~sink.vsync)
        else:
            self.comb += pads.vsync.eq(sink.vsync)

        # Drive Datas.
        cbits  = len(pads.r)
        cshift = (8 - cbits)
        for i in range(cbits):
            self.comb += pads.r[i].eq(sink.r[cshift + i] & sink.de)
            self.comb += pads.g[i].eq(sink.g[cshift + i] & sink.de)
            self.comb += pads.b[i].eq(sink.b[cshift + i] & sink.de)

[enjoy-digital]

Thanks @suarezvictor, we are indeed using a DDR primitive on Xilinx even for SDR output (https://github.com/enjoy-digital/litex/blob/master/litex/build/xilinx/common.py#L305-L308). This would need to be adapted or ODDR support for nextpnr+Xilinx implemented.