enjoy-digital / litex

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Sipeed tang nano 9k uart problem #1644

Closed mgaletakis closed 1 year ago

mgaletakis commented 1 year ago

Hello,

I am trying to test litex on sipeed tang_nano_9k board. Litex is installed on WSL on windows and tested with various board like the digilent arty-7. The sipped board seems to be programmed and alive i.e the ledchaser works but nothing happens on the serial port it is stacked. The board hardware is ok if i program it with gowin software with a uart demo it works fine both in windows and WSL.

Did someone else had similar problems? Any hints ? Thank you in advance M

trabucayre commented 1 year ago

Your issue seems similar to this one. Could you try proposed test? Thanks.

mgaletakis commented 1 year ago

Yes i will try it first thing Monday morning (hardware is in my office) and maybe try also to move rom section in ram Thank you i will get back with results soon M

trabucayre commented 1 year ago

I have modified target to remove

kwargs["integrated_rom_size"] = 0

and

self.bus.add_region("rom", SoCRegion(
    origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
    size   = 64*kB,
    linker = True)
)
self.cpu.set_reset_address(self.bus.regions["rom"].origin)

it's confirm my assumption:

ERROR (RP0002) : The number(31) of BSRAM in the design exceeds the resource limit(26) of current device. And RAM_STYLE maybe the useful user assignment to change the inference result

This why the rom must be stored into the flash.

mgaletakis commented 1 year ago

Hi @trabucayre The board is working fine if you use flash form bios. I am using WSL on windows and openFPGAloader. Also, as mentioned in the other issue you pointed, the flashing procedure is slow. litex

Thank you for your support i will close this issue if you agree.

trabucayre commented 1 year ago

Thanks for your feedback! Yes, as mentionned in the other issue with litlebee devices configured in on-chip mode the SPI flash access must be done in JTAG Boundary Scan Mode (see [UG290E](http://cdn.gowinsemi.com.cn/UG290E.pdf p.58). In this mode the SPI flash is bitbanged an consecuently time to program is awfully slow.

You can close it yep :)

luxuan12512 commented 11 months ago

合作 hello,i have quetion about it . i dele the del the code

kwargs["integrated_rom_size"] = 0

and

self.bus.add_region("rom", SoCRegion( origin = self.bus.regions["spiflash"].origin + bios_flash_offset, size = 64*kB, linker = True) ) self.cpu.set_reset_address(self.bus.regions["rom"].origin)

and run in terminal: ./sipeed_tang_nano_9k.py --build is no problem,and uart is out but run in termimal: ./sipeed_tang_nano_9k.py --with-spi-sdcard --build have error ERROR (RP0002) : The number(31) of BSRAM in the design exceeds the resource limit(26) of current device. And RAM_STYLE maybe the useful user assignment to change the inference result

if i don't del the code to run : ./sipeed_tang_nano_9k.py --with-spi-sdcard --build is no error but uart isn't out

So what should I do to be able to have urat output in the --with-spi-sdcard thanks!!!

Jiraphat-DEV commented 8 months ago

Hello, I have the same problem as you. And I read and still don't understand how to fix this problem. Can you please explain it to me? Thank you very much