gsomlo
commented
1 year ago On Thu, Aug 17, 2023 at 06:34:49AM -0700, Norbert Kremeris wrote:
I can confirm that it boots fine when used with Litex sim when the rocket is regenerated with the following configurations:
class LitexConfig_linux_1_1 extends Config( new WithNBigCores(1) ++ new WithEdgeDataBits(64) ++ new WithInclusiveCache() ++ new BaseLitexConfig )
class LitexConfig_linux_1_2 extends Config( new WithNBigCores(1) ++ new WithEdgeDataBits(128) ++ new WithInclusiveCache() ++ new BaseLitexConfig )
I have a very stupid, basic question: how did you "connect" the
L2 InclusiveCache and RocketChip sources? I.e., where did you copy
the rocket-chip-inclusive-chache git repo w.r.t. the rocket-chip repo,
and what (if any) files did you edit to "link" them, before adding
"WithInclusiveCache()" to your chosen class in
rocket-chip/src/main/scala/system/Configs.scala
and running the verilog generation/elaboration, presumably via make ... CONFIG=... ?
n-kremeris
Hi All!
I'm trying to integrate the L2 InclusiveCache from ChipsAlliance (https://github.com/chipsalliance/rocket-chip-inclusive-cache) with a single Rocket core to be used inside the Litex SoC.
I can confirm that it boots fine when used with Litex sim when the rocket is regenerated with the following configurations:
And below are the cmdlines used to launch Litex sim:
litex_sim --with-sdram --sdram-data-width 64 --cpu-type rocket --cpu-variant linux --cpu-num-cores 1 --cpu-mem-width 1 --jobs 12 --threads 12litex_sim --with-sdram --sdram-data-width 128 --cpu-type rocket --cpu-variant linux --cpu-num-cores 1 --cpu-mem-width 2 --jobs 12 --threads 12Both options boot to bios without issues and successfully pass the built in memory test.
Additionally, i have tried running a tiny baremetal program using the internal verilator based rocketchip simulator (rocket-chip/emulator) and that also works with both the 64 and the 128 bit mem configuration (the application is loaded into the main_ram area)
The design with the included L2 cache works when synthesized for a real FPGA targetting the Digilent Nexys Video board, but only when using
--cpu-mem-width 1, which implicitly makes the Litex SoC builder generate a memory width adapter from 64bits to 128bits for LiteDRAM, as the Digilent Nexys video board uses 128bit wide memory bus. Below is the command used to build this version of the bitstream:./litex-boards/litex_boards/targets/digilent_nexys_video.py --build --cpu-type rocket --cpu-variant linux --cpu-num-cores 1 --cpu-mem-width 1 --sys-clk-freq 50e6 --with-ethernet --bus-data-width 64 --bus-address-width 32 --csr-csv ./csr.csvHowever, when using the Rocket variant with 128 bit memory bus width with
--cpu-mem-width 2, the bios memtest hangs upon the first write attempt and does not proceed, as can be seen below:Based on the fact that litex_sim (and rocket's internal sim) works when using L2 with memory width set to either 64 or 128, I assume there is something strange happening from the Litex.
I would really appreciate some advice on how to narrow down where the problem is, as I would like to avoid having to use the memory width adaptor. Thanks in advance!