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Running bare-metal firmware on latest CVA5 core #1963

Open Rajnesh28 opened 1 month ago

Rajnesh28 commented 1 month ago

Hi everyone,

I have added the latest CVA5 core (found here: https://github.com/openhwgroup/cva5) to pythondata-cpu-cva5 (replacing the original core contents Litex has in pythondata-cpu-cva5/pythondata-cpu-cva5/system_verilog with what's currently on the main branch of that repository).

I was able to generate an SoC using the latest version of the CVA5 core although I am having difficulty booting any code on it. I am trying to run the following script, and attempting to boot demo.bin from the demo program.

python litex_sim.py --with-sdram --sdram-init=demo.bin --cpu-type=cva5

However, the terminal freezes on liftoff. Does anyone have any idea why this might be the case, or could provide debugging tips for resolving this issue and getting bare metal firmware running on the latest version of this CPU?

image

Rajnesh28 commented 1 month ago

I am fairly new to Verilator as well, I tried to add a --trace argument to the python script, but I ended up with a vcd file that was rather large (several GBs). I'm more used to graphical simulators like ModelSim/Vivado Simulator/etc, so some tips would be more than appreciated. Also, trying to inspect what instruction is inside the Program Counter that's failing to continue or whatever, would be useful information to obtain.