no STB or CYC when reading from a 8 bit wishbone peripheral using picorv32

[dwalton65]

I have added a 8 bit wishbone peripheral as follows:

class SpiModule(Module):
    def __init__(self, platform, spi_miso, spi_mosi, spi_ss_n, spi_sclk):
        self.bus    = bus    = wishbone.Interface(data_width=8, adr_width=8)
.
.
.

class BaseSoC(SoCCore):
.
.
.
        sdrv_spi_miso = platform.request("sdrv_spi_miso")
        sdrv_spi_mosi = platform.request("sdrv_spi_mosi")
        sdrv_spi_sclk = platform.request("sdrv_spi_sclk")
        sdrv_spi_ss_n = platform.request("sdrv_spi_ss_n")
        self.submodules.sdrvspimodule = SpiModule(platform = platform,
                                            spi_miso = sdrv_spi_miso,
                                            spi_mosi = sdrv_spi_mosi,
                                            spi_sclk = sdrv_spi_sclk,
                                            spi_ss_n = sdrv_spi_ss_n)
        sdrvspimodule_region = SoCRegion(origin=0xc8000000, size=32, cached=False)
        self.bus.add_slave(name="sdrvspimodule", slave=self.sdrvspimodule.bus, region=sdrvspimodule_region)

This was build with ./test_ulx3s_target.py --build --device=LFE5U-85F --cpu-type=picorv32 --cpu-variant=standard --csr-csv=build/csr.csv --ecppack-compress

A single byte write to address 0x0c appears to work:

However a single byte read from address 0x0c never asserts STB or CYC

For comparison, this is a single byte read from address 0x0c using the vexriscv CPU:

[enjoy-digital]

Thanks @dwalton65, I'll do a simulation and try to fix if issue.