migen/LiteX generates code which disconnects LED outputs in yosys

[hansfbaier]

I have this test design for GTP transceivers, which contains a counter and LEDs driven by the TX clock. Unfortunately with this kind of writing the migen code: https://github.com/openXC7/primitive-tests/blob/b7dc9ee74939133fc45c76dff732660344580384/gtp_channel/gtp_channel.py#L101 This generates the following Verilog code:

[...]
always @(*) begin
    user_led0 <= 1'd0;
    user_led1 <= 1'd0;
    user_led2 <= 1'd0;
    user_led3 <= 1'd0;
    {user_led3, user_led2, user_led1, user_led0} <= slice_proxy0;
    {user_led3, user_led2, user_led1, user_led0} <= slice_proxy1;
    {user_led3, user_led2, user_led1, user_led0} <= slice_proxy2;
    {user_led3, user_led2, user_led1, user_led0} <= slice_proxy3;
end
[...]
always @(*) begin
    slice_proxy0 <= 4'd0;
    slice_proxy0[0] <= counter[24];
end
always @(*) begin
    slice_proxy1 <= 4'd0;
    slice_proxy1[1] <= gpll_lock;
end
always @(*) begin
    slice_proxy2 <= 4'd0;
    slice_proxy2[2] <= 1'd0;
end
always @(*) begin
    slice_proxy3 <= 4'd0;
    slice_proxy3[3] <= 1'd0;
end
[...]

The LEDs are hardwired to zero after this is synthesized for Xilinx in yosys:

[enjoy-digital]

Thanks @hansfbaier, this could be a minimal repro of an issue we saw with LiteEth/OpenXC7 a few weeks ago. We'll look at it with @trabucayre.

[hansfbaier]

That's what I thought