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build: efinix: common.py; add `SDRInput` #2081

Closed maass-hamburg closed 2 months ago

maass-hamburg commented 2 months ago

add SDRInput for efinix

enjoy-digital commented 2 months ago

Thanks, this is merged.

enjoy-digital commented 2 months ago

@maass-hamburg: I had to disable it for now with https://github.com/enjoy-digital/litex/commit/b135f7151216960013d75dc7e8db38ff78d9177b since breaking a design the RMII Ethernet PHY, we'll have a look.

maass-hamburg commented 2 months ago

@enjoy-digital maybe it's a timing problem. Maybe try to driving the ref_clk via a ClkOutput directly from the PLL with a phase of 90° to the ethernet clock. That's what we are doing and it's working.

enjoy-digital commented 2 months ago

@maass-hamburg: It's a build issue with verilog/iface.py not correctly generated, but I haven't had the time to look at it more closely yet. Probably not related to the change itself.