Open snowprogrammer opened 2 weeks ago
Hi @snowprogrammer,
are you able to build the design with --build
? That's possible a part of the code create a combinatorial loop that would need to be examined/removed. Can you look if you have a warning regarding this while building with Vivado?
Hi @snowprogrammer,
are you able to build the design with
--build
? That's possible a part of the code create a combinatorial loop that would need to be examined/removed. Can you look if you have a warning regarding this while building with Vivado?
Hello. I can build the design with --build
and the implementation with demo.bin can work, only the Verilog file is not correctly generated. In Vivado I usexsim -tp -tl
and find 6 loops in the architecture. Because I'm not familiar with this architecture, I haven't fixed the problem.
python3 -m litex_boards.targets.digilent_basys3 --integrated-rom-init=test.bin --integrated-main-ram-size=0x2000 --build
, then I test the Verilog file, and it works well in simulation in Vivado.python3 -m litex_boards.targets.digilent_basys3 --integrated-rom-init=test.bin --integrated-main-ram-size=0x2000 --bus-standard axi-lite --build
, while I launch the simulation, there is an error : FATAL_ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 1493 ns Iteration: 10000