litex_sim hangs when adding a call to a function in libliteeth

To reproduce:

litex_sim.py --with-ethernet --local-ip 192.168.2.50 --remote-ip 192.168.2.100 --integrated-main-ram-size=0x10000 --cpu-type=vexriscv --no-compile-gateware
BUILD_DIR=../build/sim make -C demo clean all
litex_sim.py --with-ethernet --local-ip 192.168.2.50 --remote-ip 192.168.2.100 --integrated-main-ram-size=0x10000 --cpu-type=vexriscv --ram-init=demo/demo.bin

This needs to be run with the patch below, on main.c

10a11
> #include <libliteeth/udp.h>
204a206,209
> #ifdef CSR_ETHMAC_BASE
>     printf("foo\n");
>     eth_init();
> #endif

This should hang, right after


[clocker] loaded
[jtagremote] loaded (0x555cc8604ef0)
[xgmii_ethernet] loaded (0x555cc8604ef0)
[gmii_ethernet] loaded (0x555cc8604ef0)
[serial2console] loaded (0x555cc8604ef0)
[serial2tcp] loaded (0x555cc8604ef0)
[ethernet] loaded (0x555cc8604ef0)
[spdeeprom] loaded (addr = 0x0)
[clocker] sys_clk: freq_hz=1000000, phase_deg=0

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2024 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Oct 29 2024 18:48:01
 BIOS CRC passed (98c60667)

 LiteX git sha1: fd9c636e7

--=============== SoC ==================--
CPU:        VexRiscv @ 1MHz
BUS:        wishbone 32-bit @ 4GiB
CSR:        32-bit data
ROM:        128.0KiB
SRAM:       8.0KiB
MAIN-RAM:   64.0KiB

--========== Initialization ============--

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Executing booted program at 0x40000000

--============= Liftoff! ===============--

Any thoughts?

enjoy-digital / litex

litex_sim hangs when adding a call to a function in libliteeth #2110