Closed juiceRv closed 2 weeks ago
litex_sim --cpu-type=picorv32 --sim-debug --gtkwave-savefile --trace --trace-fst --with-sdram --sdram-module MT48LC16M16 --sdram-data-width 32 --soc-csv csr.csv
Once the simulation is running, execute the following trace commands:
trace
sdram_init
trace
finish
Thanks @juiceRv!
Description
During my testing of LiteX simulations using Verilator, I discovered that when the BIOS executes the
finish
command to properly terminate the simulation, the FST files were not being closed correctly. This resulted insim.fst
andsim.fst.hier
not being merged properly.Changes
finish
command is executed.Testing
finish
command, the FST files close correctly and the waveform files merge as expected.Additional Information
Thank you to the authors for designing such an excellent project with LiteX! I hope this fix can be accepted upstream.