enjoy-digital
commented
4 years ago Hi,
here is some code i prototyped some time ago (but haven't tested it on hardware).
This is designed to be used with SPIMaster (https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/spi.py) and the idea is read data from Wishbone, write it to SPI and be able to control this DMA from the CPU:
from migen import *
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import wishbone
SPI_START = (1<<0)
SPI_LENGTH = (1<<8)
SPI_DONE = (1<<0)
class Wishbone2SPIDMA(Module, AutoCSR):
def __init__(self):
# Wishbone
self.bus = bus = wishbone.Interface()
# Control
self.start = CSR()
self.done = CSRStatus()
# Read parameters: base and length of DMA
self.read_base = CSRStorage(32)
self.read_length = CSRStorage(32)
# SPI parameters: address of control/status/mosi registers
self.spi_control_reg_address = CSRStorage(32)
self.spi_status_reg_address = CSRStorage(32)
self.spi_mosi_reg_address = CSRStorage(32)
# # #
# Shorten CSR's names
start = self.start.re
done = self.done.status
read_base = self.read_base.storage[2:]
read_length = self.read_length.storage[2:]
spi_mosi_reg_address = self.spi_mosi_reg_address.storage
spi_control_reg_address = self.spi_control_reg_address.storage
spi_status_reg_address = self.spi_status_reg_address.storage
# internals
offset = Signal(32)
data = Signal(32)
# fsm
self.submodules.fsm = fsm = FSM()
fsm.act("IDLE",
If(start,
NextValue(offset, 0),
NextState("WISHBONE-READ-DATA")
).Else(
done.eq(1),
)
)
fsm.act("WISHBONE-READ-DATA",
bus.stb.eq(1),
bus.cyc.eq(1),
bus.adr.eq(read_base + offset),
If(bus.ack,
NextValue(data, bus.dat_r),
NextState("SPI-WRITE-DATA")
)
)
fsm.act("SPI-WRITE-DATA",
bus.stb.eq(1),
bus.cyc.eq(1),
bus.we.eq(1),
bus.adr.eq(spi_mosi_reg_address),
bus.dat_w.eq(data),
If(bus.ack,
NextState("SPI-WRITE-START")
)
)
fsm.act("SPI-WRITE-START",
bus.stb.eq(1),
bus.cyc.eq(1),
bus.we.eq(1),
bus.adr.eq(spi_control_reg_address),
bus.dat_w.eq(SPI_START),
If(bus.ack,
NextState("SPI-WAIT-DONE")
)
)
fsm.act("SPI-WAIT-DONE",
bus.stb.eq(1),
bus.cyc.eq(1),
bus.adr.eq(spi_status_reg_address),
If(bus.ack,
If(bus.dat_r & SPI_DONE,
NextState("INC-OFFSET")
)
)
)
fsm.act("INC-OFFSET",
If(offset >= read_length,
NextState("IDLE")
).Else(
NextValue(offset, offset + 1),
NextState("WISHBONE-READ-DATA")
)
)
if __name__ == '__main__':
dut = Wishbone2SPIDMA()
def dut_tb(dut):
yield dut.bus.ack.eq(1) # always ack
yield dut.bus.dat_r.eq(1) # always return 1
# configure DMA
yield dut.read_base.storage.eq(0x10000000)
yield dut.read_length.storage.eq(0x100)
yield dut.spi_mosi_reg_address.storage.eq(0x20000000)
yield dut.spi_control_reg_address.storage.eq(0x20000004)
yield dut.spi_status_reg_address.storage.eq(0x20000004)
yield
# start DMA
yield dut.start.re.eq(1)
yield
yield dut.start.re.eq(0)
yield
# wait DMA
while (yield dut.done.status) == 0:
yield
run_simulation(dut, dut_tb(dut), vcd_name="wb2spi_dma.vcd")To integrate it in your design, in your SoC:
# SPI Master
self.submodules.spi = SPIMaster(pads, 32, sys_clk_freq, spi_clk_freq)
self.add_csr("spi")
#SPI DMA
self.submodules.spi_dma = Wishbone2SPIDMA()
self.add_csr("spi_dma")
self.bus.add_master(self.spi_dma.bus).You will then need to write the CPU software to configure the address of the SPI Master registers of your design and program the DMA transfer.
kamejoko80
francis2tm
Hello,
I'd like to connect FPGA with the Silabs WF200 Wifi controller. From the IC spec, it basically requires SPI or SDIO bus interface. First of all, I want to try with SPI because it is simple, but I don't know how configure SPI with DMA to increase the performance. Is there any reference design including gateware and firmware to build a Vexrisc-V system with SPI and DMA?
Thank you.