enjoy-digital
commented
4 years ago Hi @0ena ,
The nexys4ddr.v is the indeed the generated design and it's not currently possible to split it in separate verilog files. That would indeed be useful to simplify checking the generated code (and to keep hierarchy), that's something we'd like to improve/explore on the future. It's possible to export modules individually with generators:
- https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_gen.py
- https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py
- https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py but this is still a manual process.
Regards,
Florent
Hi,
I am following this link: http://www.contrib.andrew.cmu.edu/~somlo/BTCP/ to create a RISC-V SoC that will be able to run Linux on it. I am using as a template the Nexys4DDR.
I can see that at the end of the flow, along with the bitstream there is another Verilog file created, called "nexys4ddr.v". Is this the final netlist of the placed and routed design?
If so, is there a way to create separate Verilog files for all of the submodules and not just a single one that includes everything?
Thank you in advance for your response and help.
Kind regards, Nassos