cpu-type=cv32e40p compile error

UA3MQJ commented 3 years ago

./cyclone_ep4ce10.py --cpu-type=cv32e40p --cpu-variant=standard --integrated-rom-size=0x8000

INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2020-12-18 01:05:25)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : EP4CE10E22C8.
INFO:SoC:System clock: 50.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCCSRHandler:cpu CSR allocated at Location 1.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 2.
INFO:SoCCSRHandler:uart_phy CSR allocated at Location 3.
INFO:SoCCSRHandler:uart CSR allocated at Location 4.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 5.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:CycloneIVPLL:Creating CycloneIVPLL, speedgrade -7.
INFO:CycloneIVPLL:Registering Single Ended ClkIn of 50.00MHz.
INFO:CycloneIVPLL:Creating ClkOut0 sys of 50.00MHz (+-10000.00ppm).
INFO:CycloneIVPLL:Creating ClkOut1 sys_ps of 50.00MHz (+-10000.00ppm).
INFO:SoCCSRHandler:sdram CSR allocated at Location 6.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x02000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:CycloneIVPLL:Config:
n          : 1
clk0_freq  : 50.00MHz
clk0_divide: 26
clk0_phase : 0.00°
clk1_freq  : 50.00MHz
clk1_divide: 26
clk1_phase : 90.00°
vco        : 1300.00MHz
m          : 26
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (3)
rom                 : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram                : Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
main_ram            : Origin: 0x40000000, Size: 0x02000000, Mode: RW, Cached: True Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (3)
- rom
- sram
- main_ram
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (7)
- ctrl           : 0
- cpu            : 1
- identifier_mem : 2
- uart_phy       : 3
- uart           : 4
- timer0         : 5
- sdram          : 6
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart   : 0
- timer0 : 1
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:csr Region added at Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 4).
make: Entering directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/libcompiler_rt'
 CC       umodsi3.o
 CC       udivsi3.o
 CC       divsi3.o
 CC       modsi3.o
 CC       comparesf2.o
/home/sea/risc-v/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data/lib/builtins/comparesf2.c:85:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
 FNALIAS(__cmpsf2, __lesf2);
 ^~~~~~~
 CC       comparedf2.o
/home/sea/risc-v/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data/lib/builtins/comparedf2.c:85:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
 FNALIAS(__cmpdf2, __ledf2);
 ^~~~~~~
 CC       negsf2.o
 CC       negdf2.o
 CC       addsf3.o
 CC       subsf3.o
 CC       mulsf3.o
 CC       divsf3.o
 CC       lshrdi3.o
 CC       muldi3.o
 CC       divdi3.o
 CC       ashldi3.o
 CC       ashrdi3.o
 CC       udivmoddi4.o
 CC       floatsisf.o
 CC       floatunsisf.o
 CC       fixsfsi.o
 CC       fixdfdi.o
 CC       fixunssfsi.o
 CC       fixunsdfdi.o
 CC       adddf3.o
 CC       subdf3.o
 CC       muldf3.o
 CC       divdf3.o
 CC       floatsidf.o
 CC       floatunsidf.o
 CC       floatdidf.o
 CC       fixdfsi.o
 CC       fixunsdfsi.o
 CC       clzsi2.o
 CC       ctzsi2.o
 CC       udivdi3.o
 CC       umoddi3.o
 CC       moddi3.o
 CC       ucmpdi2.o
 CC       mulsi3.o
 AR       libcompiler_rt.a
make: Leaving directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/libcompiler_rt'
make: Entering directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/libbase'
 CC       crt0.o
 CC       exception.o
 CC       libc.o
 CC       errno.o
 CC       crc16.o
 CC       crc32.o
 CC       console.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       qsort.o
 CC       strtod.o
 CC       spiflash.o
 CC       strcasecmp.o
 CC       i2c.o
 CC       div64.o
 CC       progress.o
 CC       memtest.o
 CC       sim_debug.o
 CC       vsnprintf.o
 AR       libbase.a
 CC       vsnprintf-nofloat.o
 AR       libbase-nofloat.a
make: Leaving directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/libbase'
make: Entering directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/liblitedram'
 CC       sdram.o
 CC       bist.o
 AR       liblitedram.a
make: Leaving directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/liblitedram'
make: Entering directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/libliteeth'
 CC       udp.o
 CC       tftp.o
 CC       mdio.o
 AR       libliteeth.a
make: Leaving directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/libliteeth'
make: Entering directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/liblitespi'
 CC       spiflash.o
 AR       liblitespi.a
make: Leaving directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/liblitespi'
make: Entering directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/libfatfs'
 CC       ffunicode.o
 CC       ff.o
 AR       libfatfs.a
make: Leaving directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/libfatfs'
make: Entering directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/liblitesdcard'
 CC       sdcard.o
 CC       spisdcard.o
 AR       liblitesdcard.a
make: Leaving directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/liblitesdcard'
make: Entering directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/liblitesata'
 CC       sata.o
 AR       liblitesata.a
make: Leaving directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/liblitesata'
make: Entering directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/bios'
 CC       isr.o
 CC       boot-helper.o
 CC       boot.o
 CC       helpers.o
 CC       cmd_bios.o
 CC       cmd_mem.o
 CC       cmd_boot.o
 CC       cmd_i2c.o
 CC       cmd_spiflash.o
 CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       cmd_litesata.o
 CC       main.o
 CC       complete.o
 CC       readline.o
 LD       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/bios/../include/generated/regions.ld riscv64-unknown-elf

ROM usage: 17.94KiB     (56.06%)
RAM usage: 1.63KiB  (20.41%)

make: Leaving directory '/home/sea/risc-v/litex-boards/litex_boards/targets/build/cyclone_ep4ce10/software/bios'
Traceback (most recent call last):
  File "./cyclone_ep4ce10.py", line 101, in <module>
    main()
  File "./cyclone_ep4ce10.py", line 94, in main
    builder.build(run=args.build)
  File "/home/sea/risc-v/litex/litex/soc/integration/builder.py", line 217, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/sea/risc-v/litex/litex/soc/integration/soc.py", line 1069, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/sea/risc-v/litex/litex/build/altera/platform.py", line 36, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/sea/risc-v/litex/litex/build/altera/quartus.py", line 210, in build
    _build_qsf(
  File "/home/sea/risc-v/litex/litex/build/altera/quartus.py", line 102, in _build_qsf
    qsf.append(tpl.format(lang=language.upper(), path=filename.replace("\\", "/"), lib=library))
AttributeError: 'NoneType' object has no attribute 'upper'

Disasm commented 3 years ago

Additional info: this happens because cv32e40p provides a file with .svh extension which is added to the source list with language None. For this file LiteX also generates a load_None command for yosys. This CPU also fails to build with yosys, because LiteX generates a load_systemverilog command for other files that doesn't exist (load_verilog -sv should be used instead).

mithro commented 3 years ago

@kgugala - As @antmicro added this core, can you assign someone to look into this?

kgugala commented 3 years ago

This seems to be a generic issue with SV sources in Intel targets. I'll get somebody to check it

kgugala commented 3 years ago

@UA3MQJ where can I find the cyclone_ep4ce10.py target? I don't see it neither in LiteX nor in litex-boards

Disasm commented 3 years ago

@kgugala you can use ./de10lite.py --cpu-type=cv32e40p to reproduce the issue.

kgugala commented 3 years ago

I opened #738 fixing the crash reported here. With this one LiteX seems to generate correct qsf. However, Quartus does not seem to be able to elaborate cv32e40p sources - it complains about bunch of syntax errors. I suppose this should be discussed upstream (in cv32e40 repo)

kgugala commented 3 years ago

I tested this with QuartusLite 20.1

enjoy-digital commented 3 years ago

Thanks @kgugala, @Disasm. I agree with @kgugala that we should first be sure the CPU can be compiled correctly with Quartus.

UA3MQJ commented 3 years ago

Thanks! There are no errors by Litex now. Remain only synthesis errors in Quartus.

Error (10170): Verilog HDL syntax error at riscv_id_stage.sv(937) near text: "genvar";  expecting an identifier ("genvar" is a reserved keyword ). Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/sea/risc-v/pythondata-cpu-cv32e40p/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_id_stage.sv Line: 937
Error (10112): Ignored design unit "riscv_id_stage" at riscv_id_stage.sv(40) due to previous errors File: /home/sea/risc-v/pythondata-cpu-cv32e40p/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv_id_stage.sv Line: 40
Info (12021): Found 0 design units, including 0 entities, in source file /home/sea/risc-v/pythondata-cpu-c

enjoy-digital / litex

cpu-type=cv32e40p compile error #733