search

enjoy-digital / litex

Build your hardware, easily!
Other
2.9k stars 556 forks source link

ULX3S: Adding spiflash, U3 pinout error. #771

Closed blakesmith closed 3 years ago

blakesmith commented 3 years ago

Not sure if I should open this issue here, or on some other ULX3S repo...

I'm attempting to add the onboard SPI flash to the ULX3S board to enable my SoC to boot from flash (See initial WIP commit here: https://github.com/blakesmith/litex-boards/commit/2859975144bbb5a4a872ca690dfb7907fbd8b8af#diff-0d05f744fae28b2e373b10e5bc6eda679ce414f074620c726c5044e1071ed72eR87). Relevant snippet is here:

    # SPIFlash
    ("spiflash", 0,
        Subsignal("cs_n", Pins("R2")),
        Subsignal("clk", Pins("U3")),
        Subsignal("miso", Pins("V2")),
        Subsignal("mosi", Pins("W2")),
        Subsignal("wp", Pins("Y2")),
        Subsignal("hold", Pins("w1")),
        IOStandard("LVCMOS33")
    ),
    ("spiflash4x", 0,
        Subsignal("cs_n", Pins("R2")),
        Subsignal("clk", Pins("U3")),
        Subsignal("dq", Pins("W2", "V2", "Y2", "W1")),
        IOStandard("LVCMOS33")
    ),

I followed the schematics here, but the "U3" pin is not present in the CABGA381 package, and get a constraint error:

Info: Packing IOs..                                                                     
Info: pin 'clk25$tr_io' constrained to Bel 'X0/Y47/PIOA'.                               
Info: pin 'oled_ctl_csn$tr_io' constrained to Bel 'X0/Y89/PIOA'.                                                                                                                
Info: pin 'oled_ctl_dc$tr_io' constrained to Bel 'X0/Y92/PIOA'.                                                                                                                 
Info: pin 'oled_ctl_resn$tr_io' constrained to Bel 'X0/Y92/PIOB'.                                                                                                               
Info: pin 'oled_spi_clk$tr_io' constrained to Bel 'X0/Y92/PIOD'.                        
Info: pin 'oled_spi_mosi$tr_io' constrained to Bel 'X0/Y92/PIOC'.                       
Info: pin 'rst$tr_io' constrained to Bel 'X4/Y95/PIOA'.                                 
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X126/Y89/PIOA'.                       
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X126/Y38/PIOC'.                         
Info: pin 'sdram_clock$tr_io' constrained to Bel 'X126/Y38/PIOB'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X126/Y86/PIOA'.                                                                                                                
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X126/Y86/PIOB'.                       
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X126/Y86/PIOC'.                        
Info: pin 'serial_rx$tr_io' constrained to Bel 'X0/Y89/PIOB'.                           
Info: pin 'serial_tx$tr_io' constrained to Bel 'X0/Y56/PIOC'.                           
ERROR: IO pin 'spiflash_clk$tr
_io' constrained to pin 'U3', which does not exist for package 'CABGA381'.
ERROR: Packing design failed.

Here's a screenshot from schematic as well:

Screenshot from 2021-01-07 17-46-14

I validated that that pin does not exist in the latest Trellis DB:

blake@blake-XPS-13-9360:~/src/prjtrellis/database/ECP5/LFE5UM5G-85F$ cat iodb.json | jq .packages.CABGA381.U3
null

I can't seem to find an ECP5 caBGA381 pinout diagram (just spreadsheets / CSVs) to see if the pin just has a different name from the footprint used on the board, from the one it's actually tied to.

Any advice on how to proceed here? This seem unlikely to be an issue in the Trellis Database (though it could be!) Happy to open this on a ULX3S repo if that's more appropriate.

Thanks so much for LiteX! I'm really enjoying exploring it so far.

blakesmith commented 3 years ago

Closing in favor of: https://github.com/litex-hub/litex-boards/issues/148