search

enjoy-digital / litex

Build your hardware, easily!
Other
2.99k stars 567 forks source link

Verilator trace is never written to disk properly #831

Open techninja1008 opened 3 years ago

techninja1008 commented 3 years ago

I've been trying to get my design to simulate properly with Verilator using SimPlatform. I've discovered, however, that the outputted VCD file is at best malformed (with GTKWave refusing to open it) and often completely empty.

Browsing through the harness code shows that neither of tfp->close() or tfp->flush() are present, meaning that the trace file isn't written even when the simulation finishes naturally. I've found that adding VerilatedVcd::flush_all(); at the end of litex_sim_dump() in sim_init.cpp and manually building and running the simulation results in a working trace file.

nickoe commented 3 years ago

@techninja1008 Could this be, maybe tangentially, related to https://github.com/enjoy-digital/litex/issues/712 ?

techninja1008 commented 3 years ago

As far as I can tell, that issue does not seem to be related to this one. In this case, dump() is called correctly and successfully however the file is never flushed to disk.

nickoe commented 3 years ago

@techninja1008 Can you reproduce this with litex_sim.py? If so, what commandline args do you use? I think we need an easy way to reproduce your steps to make progress on this.

troibe commented 3 years ago

I also encountered this issue a few times (seems to be flaky). After applying vcd2fst I could view the malformed VCD files. Next time it occurs I will share the arguments.

GuzTech commented 3 years ago

I have the same issue as the OP. To reproduce, simply run litex_sim.py using upstream LiteX. In my case, the contents of the VCD file just stops abruptly, indicating the non-existence of a flush or something similar.

FATHY174 commented 1 year ago

I have the same issue. I try running litex_simualtion and running the SDRAM test but nothing is happening in the VCD file,I run it in GTKwave but it only has variables and no simulations.

I use (New_Litex_venv) $ verilator --version Verilator 4.028 2020-02-06 rev v4.026-92-g890cecc1 (New_Litex_venv)$ litex_sim --cpu-type=vexriscv --with-sdram --gtkwave-savefile Is there are arguments I am not using or there is a bug in LITEX that produces VCD files with no simulations? is there any solution for this issue?

krabo0om commented 1 year ago

I'm facing the same issue, the VCD is void of any updates, only the signal definitions. Is there any fix or known work around?