Prepare PoC on Arty/KCU105 and verify > 1GB access.

As described in https://github.com/enjoy-digital/litex/issues/1844, the PoC will demonstrates mapping of > 1GB of DRAM to the 64-bit SoC:

[x] Prepare design with UARTBone + CPU and DRAM on Arty mapped to regular LiteX region + > 4GB region. Demonstrate access by the CPU to the first region and trough UARTBone to the two regions.
[x] Prepare design with UARTBone + CPU and DRAM on KC705 mapped to regular LiteX region + > 4GB region. Demonstrate access by the CPU to the first region (<1GB addressed) and trough UARTBone to the two regions (with > 1GB on the higher region to demonstrate that > 1GB can be effectively mapped).

enjoy-digital / litex_64bit_addressing_test