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enjoy-digital / litex_agilex5_test

Initial Test/Support of LiteX on Intel Agilex5 FPGAs.
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Tunning frequency #10

Closed Dolu1990 closed 2 months ago

Dolu1990 commented 3 months ago

Hi,

I'm trying to tune a bit the SoC frequency, it seems it is all driven by ed_synth/emif_phy2_inst/usr_clk right ? I tried tunning it via litex --sys-clk-freq 200000000, it seems things aren't connected.

What would be the procedure to change the SoC frequency ?

enjoy-digital commented 3 months ago

Hi @Dolu1990,

for now the sys_clk is indeed related to the DRAM controller frequency (as with LiteDRAM), but here as you correctly saw, the DRAM controller frequency is providing the frequency (that's the opposite with LiteX/LiteDRAM). To have more flexibility, we could add an AXI CDC between the CPU and DRAM, but there are probably more interesting points to look at first to have improve DRAM access effiency.

@Dolu1990: We'll be off for the next 2 weeks, could we look at this together at the end of August.

Dolu1990 commented 3 months ago

We'll be off for the next 2 weeks, could we look at this together at the end of August.

Sure, i will meanwhile do some VexiiRiscv/NaxRiscv specific fmax tests without the full SoC.

enjoy-digital commented 2 months ago

With https://github.com/enjoy-digital/litex_agilex5_test/issues/14, it will be possible to change sys_clk_freq.

enjoy-digital commented 2 months ago

A PLL is now integrated in the design through a Quartus IP. This already allow running the CPU at 220MHz and the DRAM at a different frequency. More flexibility will be offered when #14 will be implemented. We can close this issue and keep track of things in #14.