FMax measurements

[Dolu1990]

Hi,

Here is were i'm reporting the FMax mesurments and progress.

For VexiiRiscv (set as toplevel, after some tunning) with :

• RV32IMACSU + 4*4KB I$ + 4*4KB D$ + D$ hardware prefetcher + store buffer + MMU + BTB + GShare + RAS + performance counters*4
• ~1.55 dhrystone/Mhz
• Artix 7 speed grade 3 -> 190 Mhz 5452 LUT
• Agilex V speed grade 4 -> 235 Mhz 4,303 ALMs (A5ED065BB32AI4S)

On Agilex, the FMax is limited by the multiplication unit. Without it, it goes to 260 Mhz

It seems like the the timings to go from the FPGA interconnect -> DSP(mul 17*17 -> reg) is high.

[Dolu1990]

For NaxRiscv (set as toplevel) :

• RV32IMACSU + 4x4KB I$ + 4x4KB D$ + 64xROB + 16xLQ + 16xSQ + MMU + BTB + GShare + RAS + performance countersx4
• ~2.9 dhrystone/Mhz (for config without RVC)
• Artix 7 speed grade 3 -> 150 Mhz 14146 LUT
• Agilex V speed grade 4 -> 209 Mhz 13890 ALMs (A5ED065BB32AI4S)

I did aswell hit the fmax limit in the multiplication unit (190 Mhz), went up to 209 Mhz after some tunning. So to explaine the multiplcation unit tunning, by default, i had KEEP attribute on the input and output registers of the multiplication as a way to avoid having the synthesis merging those register into the DSP block.

• For Artix 7 FPGA, it allowed to relax timings beyond, as those FPGA have a relatively fast DSP block mul.
• For Agilex 5, it seems that the DSP block is consuming more timings (relatively speaking) and so, removing those KEEP attribute improve timings there.

[Dolu1990]

I will be in travel for the next two weeks.

[enjoy-digital]

Thanks @Dolu1990, from what we discussed, the SpinalHDL changes to increase the FMax were still local. Have you been able to upstream them or can you update the issue when done?

[Dolu1990]

Hi @enjoy-digital,

I just pushed everything i had in hands. Also i added the --relaxed-mul-inputs option with VexiiRiscv (--vexii-args="... --relaxed-mul-inputs" This is in https://github.com/enjoy-digital/litex/pull/2059.

Overall, the main timings which created issues was :

• FF -> small comb path+routing -> DSP(mul -> FF)

That --relaxed-mul-inputs option will push the DSP mul to the second stage of the execute pipeline.

Let's me know if you have any issues.

[enjoy-digital]

Thanks @Dolu1990, I just merge https://github.com/enjoy-digital/litex/pull/2059. We'll do more test with increased freq when https://github.com/enjoy-digital/litex_agilex5_test/issues/14 will be done, allow more flexible clocking.

[Dolu1990]

Sure ^^