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enjoy-digital / litex_agilex5_test

Initial Test/Support of LiteX on Intel Agilex5 FPGAs.
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LPDDR4 AXI interfaces: decoupling clock domains #13

Closed trabucayre closed 2 months ago

trabucayre commented 2 months ago

With commit https://github.com/enjoy-digital/litex_agilex5_test/commit/dbdd2529eab33c9d4999ed291cb05bf9decab429 : configuration interface and axi4 have two distincts ClockDomain. Also, AXI4 interface and sys_clk are no more feeded by an EMIF output clock: it's now possible to select any frequency (as done by https://github.com/enjoy-digital/litex_agilex5_test/commit/702005474e0b90541edce5cef23967574fc35361).

This commit serie address issue https://github.com/enjoy-digital/litex_agilex5_test/issues/10

Here mem_test with a 220MHz sys_clk:

memtest_220MHz

Linux is also able to boot with this configuration/frequency

enjoy-digital commented 2 months ago

Done, we can close.