LPDDR4 Qsys/Example - Githubissues

enjoy-digital / litex_agilex5_test

Initial Test/Support of LiteX on Intel Agilex5 FPGAs.

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LPDDR4 Qsys/Example #3

Closed trabucayre closed 2 months ago

trabucayre commented 4 months ago

An example of gateware with LPDDR4 is available in examples/bts_emif/bts_ddr4_2b from agilex5e_prem_es_a5ed065bb32ae6sr0_qii24.1b115_v1.3.zip archive.

examples/bts_emif directory also contains a .docx: must be read to fix errors due to absolute path used in the gateware

The .docx explains how to fix .qprs (RAM configuration) path, but also provides a note about SWIZZLE: this section explains this part.

Refs:

external memory IP user guide

trabucayre commented 4 months ago

QSYS block looks like: lpddr4_qsys

enjoy-digital commented 2 months ago

This is now working/integrated, we can close.