search

enjoy-digital / litex_agilex5_test

Initial Test/Support of LiteX on Intel Agilex5 FPGAs.
3 stars 0 forks source link

Hardcoded paths #4

Closed Dolu1990 closed 4 months ago

Dolu1990 commented 4 months ago

I tried to run : /intel_agilex5e_065b_premium_devkit.py --bus-standard=axi-lite --cpu-type=vexiiriscv --cpu-variant=linux --vexii-args="--with-rvc --with-rvf" --with-coherent-dma --update-repo=no --synth-tool=quartus_syn --build

It error out on : qsys-generate --synthesis ./gateware/ed_synth.qsys

With : 

2024.07.10.12:50:08 Error: ed_synth_emif_ph2_inst.emif_ph2_inst: Memory Preset (MEM_PRESET_ID) has invalid value - Custom Preset. Valid values include: {No Presets Found}
2024.07.10.12:50:08 Error: ed_synth_emif_ph2_inst.emif_ph2_inst: Specified qprs file does not exist: /home/gwe/enjoydigital/intel/litex_agilex_test/gateware/lpddr_4266bin_1866.qprs
2024.07.10.12:50:08 Error: ed_synth_emif_ph2_inst.emif_ph2_inst: No presets found for this configuration. Please create a custom preset or change the high level parameters to match an existing preset.

It seems like gateware/ip/ed_synth/ed_synth_emif_ph2_inst.ip has hardcoded paths internaly : 

rawrr@rawrr-pc:/media/data2/proj/litex/agilex/litex_agilex_test$ grep -r gwe/enjoydigital
gateware/ip/ed_synth/ed_synth_emif_ph2_inst.ip:          <ipxact:value>/home/gwe/enjoydigital/intel/litex_agilex_test/gateware/lpddr_4266bin_1866.qprs</ipxact:value>
trabucayre commented 4 months ago

Must be fixed by https://github.com/enjoy-digital/litex_agilex_test/commit/7e063fd8cbd9313a197b2865a796b6ae0d82c745

Thanks to point this issue

Dolu1990 commented 4 months ago

Nice thanks :D

enjoy-digital commented 4 months ago

We can probably close this now.