Ethernet status

[trabucayre]

Build fails with:

Internal Error: Sub-system: U2B2_HVIO, File: /quartus/db/u2b2_hvio/u2b2_hvio_hviowr_translator_module.cpp, Line: 118
mux /xx20_u1/xx20_clkordat_din_1to2_demux_u8, with bcm value SEL_CLK, is trying to reset to SEL_DATA0
Stack Trace:
  Quartus          0x1e77b: U2B2_HVIO_HVIOWR_TRANSLATOR_MODULE::translate(U2B2_CONFIG*, DBCM_CHIP*) + 0x175b (db_u2b2_hvio)
  Quartus          0xfb3a9: U2B2_MODULE::translate(U2B2_CONFIG*, DBCM_CHIP*) + 0x51 (db_u2b2_core)
  Quartus          0xc2b4b: U2B2_DIRECTOR::translate_fn(U2B2_MODULE*, U2B2_CONTEXT const&, U2B2_CONFIG*) const + 0x69 (db_u2b2_core)
  Quartus          0xd4784: void tbb::detail::d1::dynamic_grainsize_mode<tbb::detail::d1::adaptive_mode<tbb::detail::d1::auto_partition_type> >::work_balance<tbb::detail::d1::start_for<tbb::detail::d1::blocked_range<unsigned long>, tbb::detail::d2::parallel_for_body_wrapper<__gnu_cxx::__normal_iterator<U2B2_CONFIG**, std::vector<U2B2_CONFIG*, std::allocator<U2B2_CONFIG*> > >, U2B2_DIRECTOR::translate(U2B2_CONTEXT const&) const::{lambda(U2B2_CONFIG*)#1}, U2B2_CONFIG*>, tbb::detail::d1::auto_partitioner const>, tbb::detail::d1::blocked_range<unsigned long> >(tbb::detail::d1::start_for<tbb::detail::d1::blocked_range<unsigned long>, tbb::detail::d2::parallel_for_body_wrapper<__gnu_cxx::__normal_iterator<U2B2_CONFIG**, std::vector<U2B2_CONFIG*, std::allocator<U2B2_CONFIG*> > >, U2B2_DIRECTOR::translate(U2B2_CONTEXT const&) const::{lambda(U2B2_CONFIG*)#1}, U2B2_CONFIG*>, tbb::detail::d1::auto_partitioner const>&, tbb::detail::d1::blocked_range<unsigned long>&, tbb::detail::d1::execution_data&) + 0x6a4 (db_u2b2_core)
  Quartus          0xda390: tbb::detail::d1::start_for<tbb::detail::d1::blocked_range<unsigned long>, tbb::detail::d2::parallel_for_body_wrapper<__gnu_cxx::__normal_iterator<U2B2_CONFIG**, std::vector<U2B2_CONFIG*, std::allocator<U2B2_CONFIG*> > >, U2B2_DIRECTOR::translate(U2B2_CONTEXT const&) const::{lambda(U2B2_CONFIG*)#1}, U2B2_CONFIG*>, tbb::detail::d1::auto_partitioner const>::execute(tbb::detail::d1::execution_data&) + 0x22e (db_u2b2_core)
  Quartus          0x24203: tbb::detail::r1::market::process(rml::job&) + 0xad3 (tbb)
  Quartus          0x1f562: tbb::detail::r1::rml::private_worker::thread_routine(void*) + 0x52 (tbb)
  System           0x8ad32: (c)
  System          0x1072ac: (c)

End-trace

Not seen this error before (during integration)

[trabucayre]

2024/08/24 Update (quartus 24.2)

Build fails with:

Error (23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: hvio_1_1
Error (12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid and the Fitter must be restarted.

We have observed:

• during 24.1 -> 24.2 migration top module has lost pll_250m_tx_clock_clk and pll_125m_tx_clock_clk (both remains present for intel_gmii_to_rgmii_adapter module)
• ADVANCED_MODE and USE_RGMII_SF can't be configured using graphic tools (USE_RGMII_SF is also not provided when intel_rgmii_module is instanciated).

[gsteiert]

Have you tried using LiteEth? I need to see how much value our IP adds for sub 2.5GE. I will still look for fixes to this.

[enjoy-digital]

@gsteiert: We are currently working on using LiteEth with a GMII PHY along with the intel_gmii_to_rgmii_adapter. This approach initially seemed simpler than implementing the RGMII PHY for the Agilex5.

[gsteiert]

Thanks, this helps focus where to look.

[gsteiert]

There are known issues with this IP. Please wait for additional information.
The issue may be with the DDIO, so it may not help to implement your own converter right now. I'll let you know when I have more details.

[trabucayre]

I have pushed an RGMII Phy (based on LiteEth's s7rgmii) using only FPGA primitives to have something easiest to debug/modify. I observe the same result/error but if I disable rx_ctl (pads + primitive) the build end successfully.

[trabucayre]

@gsteiert thanks for this information. I have tried some test around tx_ctl pad: first was to change location to see if error was related to someting specific to B20 -> No results. But this signal is the only one where the tennm_ph2_ddio_in has only one output connected: I have tried to do something (to avoid quartus optimisations) and the build end successfully. So I seems this primitive doesn't like to be half connected (but I have no idea if this issue is related to the primitive or to quartus).

[trabucayre]

2024/09/02 Update

Tx side is always working (but requires a not on clock signal applied to ddio) Rx side: globally fine but unstable (small files: ok, big files: not always ok, most of the time: ko)

RX unstabillity may be fixed by using MDIO control (see : https://www.mouser.fr/datasheet/2/912/MARV_S_A0009147335_1-2576139.pdf)

# select PAGE 2
mdio_write 0 22 2
# write page 2, register 21 bit 5 ( RGMIITimingReceive Control) to low (Receive clock transition when data transitions)
mdio_write 0 21 0x1056
# select PAGE 0
mdio_write 0 22 0
# apply software reset (page 0, register 0, bit 15)
mdio_write 0 0 0x9140

[enjoy-digital]

For now a local patch is provided to configure the PHY correctly with LiteX BIOS at startup: https://github.com/enjoy-digital/litex_agilex5_test/commit/2da75ea6a7c266fe68f321e3f4b75c7b6190d2ae We'll see to improve integration in the future but the 1Gbps RGMII + LiteEth is functionnal and usable from LiteX-BIOS or from Linux.