Random notes/observations/tests.

[enjoy-digital]

A few notes/observations/tests to do:

MiSTeR code portability:

• Generic code seems only tested with Quartus. A couple of fixes have to be done to be able to run in on Xilinx (and probably other to run with open-source tools like Yosys/Verilator/GHDL).
• To check portability, in addition of testing on Xilinx device, we could test on ECP5 (Yosys) and with LiteX-Sim (Verilator).
• Once limitation are fixed/removed, how to upstream them? Send to MiSTeR Template and let core developers pick the updates?

MiSTeR clocking portability:

• Some PLL are hardcoded for the DE10 Nano in the System and probably in the cores. To avoid modifying the cores, we could generate equivalent using LiteX and PLL wrappers.

MiSTeR / LiteX feasibility tests:

• [ ] Allow direct VGA use with LiteX Framebuffer (requires VGA capture).
• [ ] Integrate ascal.vhd with LiteDRAM.
• [ ] Add Avalon -> LiteDRAM frontend.
• [ ] Check feasilibity of SDRAM emulation with LiteDRAM/DDR3 (use Mister
• [ ] Provide different abstractions for HPS interface (To allow running MiSTeR software over Etherbone/PCIeBone, etc...) and decouple MiSTeR from Cyclone SoC.
• [ ] Try to run first cores with code untouched (except portability fixses) and just generic LiteX core wrapper + abstractions.

[hansfbaier]

The cores in the MiSTeX Github organization have already been ported to Xilinx.

[hansfbaier]

Actually last point running the first cores with portability fixes has already been done in https://github.com/MiSTeX-devel/MiSTeX-boards/ Also the Menu core already works and can load other cores. The basic functionality works. HPS interface is SPI + 3 GPIO lines