add ascal-sim.py and ascal.v

[hansfbaier]

It runs, but doesn't work yet.

[enjoy-digital]

Thanks, BTW LiteX can directly call GHDL for the VHDL -> Verilog conversion, ex: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/neorv32/core.py#L98-L171

[hansfbaier]

@enjoy-digital Wow, that is very cool.

[enjoy-digital]

This will avoid generating a verilog file per parameters config.

[hansfbaier]

@enjoy-digital I currently have a hard time to find the wishbone signals in the haystack, because migen does not seem to include AvalonMM2WishboneConverter in its name. Did I miss something? How would I do that?

[hansfbaier]

Ah I found it, it just called it 'wishbone' probably, because I called the property 'wishbone'

[hansfbaier]

Looks like the bursts in the Avalon2Wishbone bridge work This is from SimSoC

[hansfbaier]

ascal is definitely doing something

[hansfbaier]

That looks like a nice start.

[enjoy-digital]

@hansfbaier: Sorry, I'm currently working on something else, but great progress! Hope it will give you more visibility to understand the issues.

[hansfbaier]

I get this error when running ghdl with the litex converter:

vdhl-convert: ['ghdl', '--synth', '--out=verilog', '--std=08', '--no-formal', '--work=work', '-gRAMBASE=0', '-gN_AW=28', '-gN_DW=128', '-gN_BURST=64', '-e', 'ascal']
ghdl:error: unknown command option '-e'

I compiled it from git and this is the version:

$ ghdl --version
GHDL 2.0.0 (2.0.0.r0.g8185ed8) [Dunoon edition]
[...[

Ah, now it works, I forgot to add the the source file. Now it works with -e Never mind the error above

[hansfbaier]

Does LiteX have a similar converter to VHD2VConverter for amaranth? That would be great!

[hansfbaier]

I now set up the clock domains to resemble something more closer to reality. Before it was pretty much impossible for ascal to read out the memory, if the pixel clock is 100Mhz like the system clock. Weirdly enough, the video output window still seems to run at system clock, and I currently don´t (yet) understand how to make it use the "hdmi" clock domain.

[hansfbaier]

Now I got the VGA clocked right. Unfortunately with this setup the serial console crashes, if used. Because the clock in serial2console.c is hardwired to be named "sys_clk". But as soon as I use more than one clock, Verilator won't compile, because it automatically seems to rename it to sys_clk_1 because the verilog wire sys_clk already exists.

[enjoy-digital]

@hansfbaier: Thanks for the update. I'll try to have a closer look/help if I have time in the next days.

[hansfbaier]

The wishbone bridge now is in pretty good shape and the traces of this sim show some healthy interaction with the avalon port.

[hansfbaier]

I still only get a dark screen, and ascal seems to write only very little (1 burst of 8 words) to the memory in the hblanking periods. Good question why.