search

enjoy-digital / litex_mister_test

Simplification test of MiSTer with LiteX to try to help/contribute to MiSTeX project.
1 stars 1 forks source link

Test ascal.vhd with GHDL. #7

Open enjoy-digital opened 1 year ago

enjoy-digital commented 1 year ago

Could be easily done with https://github.com/enjoy-digital/litex_mister_test/issues/3 and https://github.com/enjoy-digital/litex_mister_test/issues/5 implemented.

hansfbaier commented 1 year ago

I could convert it to Verilog with rambase 0x0 AW=28 and DW=128 ascal.v.gz

hansfbaier commented 1 year ago

Also when instantiating it with Vivado, the maximum address width seems to be 28 and not 32 as the parameter range suggests, because otherwise there will be an out of range error further down in the code.