Closed mtdudek closed 4 years ago
Dolu1990
commented
4 years ago Hi,
Which board are you using ? Else, we are currently merging the SMP stuff into litex, should be done this week. I that litex merge, 4 cores worked fine for (Arty35T) I will notify you as soon this is released (very very soon) :)
Dolu1990
commented
4 years ago I tested quad core with the branch "integration", it worked fine on arty. If you want to try it you will need to update litex, and find the prebuild software binaries here : https://github.com/Dolu1990/linux-on-litex-vexriscv-prebuilt.git
I loaded it using uart.
If you change the config, you might need to install java and SBT to enable the automatic generation of the cluster which fit the parameters.
Dolu1990
commented
4 years ago Should probably go in jail :
./make.py --board=arty --cpu-count=3 --build --load
root@buildroot:~# cat /proc/cpuinfo
processor : 0
hart : 0
isa : rv32ima
mmu : sv32
uarch : spinalhdl,vexriscv
processor : 1
hart : 1
isa : rv32ima
mmu : sv32
uarch : spinalhdl,vexriscv
processor : 2
hart : 2
isa : rv32ima
mmu : sv32
uarch : spinalhdl,vexriscv
...
mtdudek
commented
4 years ago Today I was able to try again, and now everything works.
Recently I tried running vexriscv SMP with 4 cores on arty a7 35t. But I was greeted with failed memtest. I did git bisect to narrow down which commit has broken 4 core implementation, and unfortunately I found out it is this one 43aed3a. Here is log I got when I was running newest version
Number of bus errors was different between runs, as was addr errors in newest version. On the other hand on commit 43aed3a I always got 128 errors.