Closed enjoy-digital closed 2 years ago
Clock is now generated correctly with PMICs configured correctly:
python3 test_tcxo.py
Monitor TCXO cycles...
0ms : 95525386
100ms : 98293492
200ms : 101061166
300ms : 105008886
400ms : 107772799
500ms : 110541267
600ms : 115308057
700ms : 118066391
800ms : 120823657
900ms : 124666242
Frequency also seems correct but will be verified with additional tests.
Also seems correct on LiteScope capture:
Clock is now correctly configured and seen at 26MHz.
Initial support has been added to enable/check the TCXO input clock (going to the FPGA and LMS7002) but the clock does not seem to be generated. The issue is probably related to https://github.com/enjoy-digital/xtrx_julia/issues/1 that first needs to be implemented.