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enjoy-digital / xtrx_julia

XTRX LiteX/LitePCIe based design for Julia Computing
BSD 2-Clause "Simplified" License
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Improved LMS7002M PHY (now with internal TX/RX Delay). #8

Closed enjoy-digital closed 2 years ago

enjoy-digital commented 2 years ago

The LMS7002M PHY has been improved to now integrates TX/RX Clk/Data dynamic delays. This avoids using FCLK2 inversion/delays in the LMS7002M and allows higher sample-rates.

A default TX/RX delay is configured and tested with LimeSuite's CLKGEN configured to and dma loopback:

By using test/test_lms7002m_digital_interface.py script, valid delays are also found for 491.52MHZ (61.44MS/s 2 Channels MIMO) and dma loopback is also working, but the delays are different so we'll wait to have an automatic calibration feature to use this.

@maleadt: Could you try to re-generate the FPGA with this PR and verify it's also working on your side? If so, could you merge this PR?

maleadt commented 2 years ago

For the record, I could only get 61 and 122 MHz to work.

enjoy-digital commented 2 years ago

Thanks, as discussed together we'll probably have to add dynamic delays calibration to support > 122.88MHz on the various boards (a bit similar to what test_lms7002m_digital_interface.py does). For now the current sample-rate should be enough, I'll focus on this after the other features.