Closed ZanMaticPratnemer closed 7 months ago
@ZanMaticPratnemer , it is an interesting PR, I tried to run it with EVR DlyGen-1-DBusTrig-Sel
set to a 14Hz DBus bit from EVG and it gets continuously retriggered while the DBus bit is high (so half of the 14Hz cycle). Is there a way to configure it just for the DBus rising edge?
What is the application that you have been using this DBusTrig, and in which scenario? I will try to use the same config for the tests.
@zioven might have more insight into these specifics.
@zioven , @ZanMaticPratnemer, does this implementation is for the generic FPGA image e.g. mTCA-EVR-300DC-18180207.bit (or a modification)? What was the image version used during your tests?
@jerzyjamroz this is part of the standard FPGA image, is available in mTCA-EVR-300DC-18180207.bit
and even some earlier versions (we have been using this feature with stock FW since 2020).
I have also found this in the manual:
and here is an example of Jukka's implementation in his API: https://github.com/jpietari/mrf-linux-api/blob/master/api/erapi.c#L1084
@jpietari can probably elaborate since when this is available in the FW ...
@jerzyjamroz
Please review and merge if this changes are acceptable.
@jerzyjamroz can this be merger or is there anything missing from this pull request?
@zioven , nominal operation tests: https://github.com/epics-modules/mrfioc2/pull/61#issuecomment-1781255286 I will try to do that next week.
@ZanMaticPratnemer , it is an interesting PR, I tried to run it with EVR
DlyGen-1-DBusTrig-Sel
set to a 14Hz DBus bit from EVG and it gets continuously retriggered while the DBus bit is high (so half of the 14Hz cycle). Is there a way to configure it just for the DBus rising edge? What is the application that you have been using this DBusTrig, and in which scenario? I will try to use the same config for the tests.
We are testing the DBUS triggers with the following configuration:
Set the MXC4
Prescaler to provide the 10 kHz frequency
Trigger DBus bit 4
from MXC4
Output 1 [labeled DlyGen+DBus]: Triggered by Delay Generator (pulser) with following parameters
1 us
0 us
DBus bit 4
$ caget -0b TS-KG:{EVR1-DlyGen:4}DBusTrig-Sel
TS-KG:{EVR1-DlyGen:4}DBusTrig-Sel 10000
$ caget -0x TS-KG:{EVR1-DlyGen:4}DBusTrig-Sel
TS-KG:{EVR1-DlyGen:4}DBusTrig-Sel 0x10
$ caget TS-KG:{EVR1-DlyGen:4}DBusTrig-Sel
TS-KG:{EVR1-DlyGen:4}DBusTrig-Sel 16
Output 2 [labeled: DBus]: Triggered by DBus Bit 4
Add prescaler and DBus bit triggers for pulsers