Stack order ASAP

[erebuslabs]

Guys,

I need the stack order ASAP so that I can get the order started before 5 PM in Korea.

This is what they sent me:

Top-GND-PWR-Bottom

Guessing that's okay for our needs? Confirm?

[gstro]

Hey Mike! I just texted @Debrant and @dfrister because they have been the leads on the boards. It looks good to me too but I can't confirm for certain. Hopefully they get back to you soon!

[dfrister]

On it now, will have an answer in a minute or so.

[dfrister]

Top-GND-Power-Bottom appears to be the default order for the program Nathan used to design the board, but I don't know the software he used well enough to verify. Still looking.

[dfrister]

This is the stack report from the file.

Layers

Name Type Side Usage Bias Net

Top Silkscreen Silk Screen Top Non-Electrical None Top Copper Electrical Top Electrical X Documentation Documentation Top Non-Electrical None Gnd Plane Electrical Inner Electrical Power Plane GND Vcc Plane Electrical Inner Electrical Power Plane VCC Bottom Copper Electrical Bottom Electrical Y Bottom Silkscreen Silk Screen Bottom Non-Electrical None

When I spoke with Nathan he mentioned there are no blind/buried vias on the board, so I suspect it shouldn't matter which order GND and VDD are. All the vias pass both layers, and the connections should only be on the specific planes.

[dfrister]

Ok, so running a new design and specifying vdd into the upper layer does change the stack report to match. I am comfortable seeing that it means our board is Top-GND-VCC-Bot.

[erebuslabs]

Looks like that short is on the bottom of the board. I'm currently just on my phone. I'll look at the Gerber files as soon as I'm back by my computer. This one is less of a rush (we have about 18 hours :) we just had to get the process started last night to be on the books officially.

Fyi: stack order: When I chatted with the guy last night after he sent that email - from what I could make out - he confirmed what you also found. He stacked the layers both ways, but ultimately left them in the standard order. He told me we could switch it within 24hrs but that he needed a starting point (so I let him run with it until I heard from you)!

I appreciate the dedication and amount of time and work you guys are putting it. To say I'm impressed and grateful is an understatement. On May 21, 2015 7:04 AM, "Mike Borowczak" mike@erebuslabs.com wrote:

Great! There is another question that came up with a region on the board that looks like a short:

Ok, so running a new design and specifying vdd into the upper layer does change the stack report to match. I am comfortable seeing that it means our board is Top-GND-VCC-Bot.

— Reply to this email directly or view it on GitHub https://github.com/erebus-labs/blocks-o-code/issues/89#issuecomment-104154496 .

[Debrant]

Sorry guys, new job, new hours. I was sleeping.

Daniel is correct though, the board is pretty much designed to make it through even the weakest of manufacturing specs. Nothing fancy, each of the power planes has its own gerber so it shouldn't matter how they are stacked.

I just checked for the short, and could only find the crossed line of the SCL net. I will bring my laptop to work today and will check for feedback on this at lunch. Just send me the region you are looking at, either with xy coordinates or with a png.

Nice work everyone!

See you all this weekend

[erebuslabs]

It looks like it's the one in the bottom copper:

I assume it's okay since it's clearly in the bottom copper - but as late as it was last night I didn't want to screw anything up.

[Debrant]

@erebuslabs

Hey Mike, this is exactly what I figured. I am 99% sure that this is 100% ok.

It's part of the global bus that runs to each side of the board, the SCL net for IIC.

Hope this helps. My direct line is 360-448-6107

[erebuslabs]

Thanks!