Indentation gets stuck with nested else statements

[jweng2]

Multi-line "if" statements that have "else" clauses will be formatted with increasingly deep indentation which fails to reset back after closure of the "if" conditional

As an example, consider the following snippet of code which sits within a "case" statement implementing an FSM. As you can see, the first "end else begin" about midway through is indented, with all following "end" statements held to a similar indentation. This misrepresents the association of "if" statement "begins" against the closing "ends". Furthermore, the following state ADDR_SETUP is now mistakenly indented. Subsequent states in the FSM experience the same over-indentation.

        // Waiting for AHB traffic
        IDLE: begin
          // Clear out status
          xfer_done    <= 0;
          o_wrprot_err <= 0;

          // Filter out writes to invalid address space
          if (we || re) begin
            if (mr_sel[0] || mr_sel[1]) begin

              // Writes with wrprot asserted will be killed
              if (we) begin
                if (i_wr_prot) begin
                  o_wrprot_err <= 1;
                  xfer_done    <= 1;
                  end else begin
                    cs <= ADDR_SETUP;
                  end
                  end else if (re) begin
                    cs <= ADDR_SETUP;
                  end
                  end else begin
                    // release slave on invalid addr so AHB doesn't hang
                    xfer_done <= 1;
                    cs        <= AHB_DELAY;
                  end
                end
              end

              // 1st Cycle - latch in addr, drive ctrls on read
              ADDR_SETUP: begin
                cs <= WR_RD_DELAY;
                ....

I believe a cleaner and more "correct" formatting would sit along the lines of the following:

        // Waiting for AHB traffic
        IDLE: begin
          // Clear out status
          xfer_done    <= 0;
          o_wrprot_err <= 0;

          // Filter out writes to invalid address space
          if (we || re) begin
            if (mr_sel[0] || mr_sel[1]) begin

              // Writes with wrprot asserted will be killed
              if (we) begin
                if (i_wr_prot) begin
                  o_wrprot_err <= 1;
                  xfer_done    <= 1;
                end else begin
                  cs <= ADDR_SETUP;
                end
              end else if (re) begin
                cs <= ADDR_SETUP;
              end
            end else begin
              // release slave on invalid addr so AHB doesn't hang
              xfer_done <= 1;
              cs        <= AHB_DELAY;
            end
          end
        end

        // 1st Cycle - latch in addr, drive ctrls on read
        ADDR_SETUP: begin
          cs <= WR_RD_DELAY;
          ....

[GitJer]

Same problem here. It helps if the "end else begin" is broken into two lines: end else begin