WATCHDOG module

A watchdog timer (sometimes called a computer operating properly or COP timer, or simply a watchdog) is an electronic timer that is used to detect and recover from computer malfunctions. During normal operation, the computer regularly restarts the watchdog timer to prevent it from elapsing, or "timing out". If, due to a hardware fault or program error, the computer fails to restart the watchdog, the timer will elapse and generate a timeout signal. The timeout signal is used to initiate corrective action or actions. The corrective actions typically include placing the computer system in a safe state and restoring normal system operation.

watchdog

Minimal module to support watchdog timer. This module may be expanded in the future to support more robust use of the watchdog timer to monitor error conditions in the servo.

watchdog_init: Initialize the watchdog module

Clear WDRF in MCUSR.

    MCUSR &= ~(1<<WDRF);    //MCU status register and Watchdog reset flag

Write logical one to WDCE and WDE.

     WDTCSR |= (1<<WDCE) | (1<<WDE);        //To disable or change timeout: 
                                            //Simultaneously, write a logic 1 to WDCE and WDE

Turn off WDT.

    WDTCSR = 0x00;

watchdog_hard_reset: reset the device using the watchdog timer

Disable PWM to the servo motor.

    pwm_disable();
```c
- Enable the watchdog.

    WDTCSR = (1<<WDIF) |                                     // Reset any interrupt.
             (0<<WDIE) |                                     // Disable interrupt.
             (1<<WDE) |                                      // Watchdog enable.
             (0<<WDP3) | (0<<WDP2) | (0<<WDP1) | (0<<WDP0);  // Minimum prescaling - 16mS.

Wait for reset to occur.

    for (;;);

Overview of MCUSR and Watchdog Timer in AVR

The reset service routine finds out the cause of reset by examining the MCU status register (MCUSR). The contents of MCUSR are shown in figure: mcusr

WRDF: Watchdog reset flag

0 = Reset is not caused by watchdog time out.
1 = Reset is caused by watchdog time out(timer overflow). This bit is cleared by a power-on reset or writing a 0 to it.

AVR Mega Watchdog TImer(WDT)

The WDT triggers an interrupt or reset when the counter overflows.
To prevent the WDT from timing out, execute the WDR(Watchdog reset) instruction to restart the WDT.
In interrupt mode the WDT generates an interrup when the timer overflows. In system reset mode, the WDT resets the MCU when the timer expires.

The operation of WDT is controlled by the Watchdog timer control register [WDTCSR]. When Watchdog-always-on fuse is programmed, the system reset mode bit [WDE] and interrupt mode bit [WDIE] is locked to 1 and 0 respectvely, which forces the WDT to operate in system reset mode.

Contents of WDTCSR register:

Bits	7	6	5	4	3	2	1	0
WDTCSR	WDIF	WDIE	WDP3	WDCE	WDE	WDP2	WDP1	WDP0

WDIF: Watchdog interrupt flag

0 = WDT did not time out since last time it was cleared.
1 = WDT was configured in interrupt mode and a WDT time-out has ocurred. This bit is cleared by writing a 1 to it or when its service routine is entered.

WDIE: Watchdog interrupt enable

WDCE: Watchdog change enable This bit is used in timed sequences for changing WDE and prescaler bits. TO clear WDE bit and/or change the prescaler bits, WDCE must be set.

WDE: Watchdog system reset enable WDE is overriden by WRDF in MCUSR. To clear WDE, WDRF must be cleared first.

WDP3-0 : Watchdog timer prescaler.

WDCE	WDE	WDIE	Mode	Action on time-out
1	0	0	Stopped	None
1	0	1	Interrupt mode	Interrupt
1	1	0	System reset mode	Reset
1	1	1	Interrupt and system reset mode	Interrupt, then go to system reset mode
0	X	X	System reset mode	Reset

erlerobot / smart_motor

WATCHDOG module #17

WATCHDOG module

Overview of MCUSR and Watchdog Timer in AVR