The high side P-MOS need a driver to be able to control their behaviour, this would be the ? block of the figure.
P-MOS transistors are open (non-conducting) when their gate is at close to the same potential as their source, and closed (conducting) when the gate is at a significantly lower potential, i.e between 5--15V lower. This means that in order to completely turn off a high-side P-FET we’ll have to drive it’s gate as high as it’s source, which is connected to the power supply. To turn the FET on, we have to lower the gate voltage by 5…15V below Vbat.
Because at the output of the uController we have not the necessary voltage to turn off the P-MOS we need an intermediate stage between the uController and the H-bridge. We call this intermediate stage level-shifter.
Here, the gate of the small-signal N-FET is driven by a suitable logic signal (and a logic level signal can easily open this N-FET) and the drain of it is pulled up to the gate-drive power supply, Vdrive.
In our case to Vbat to turn off the P-MOS. When N-FET is driven by a logic '0' the output will be Vbat becasue it will be OFF. Else if the logic is '1' the N-FET will be open and the output will be 0V.
Summary:
Q2 and Q3 transistors behave like an inversor and make posible to turn off the P-MOS high side increasing the voltage in the P-MOS gate.
Why are needed?
Our H-bridge is similar to the next figure:
The high side P-MOS need a driver to be able to control their behaviour, this would be the ? block of the figure. P-MOS transistors are open (non-conducting) when their gate is at close to the same potential as their source, and closed (conducting) when the gate is at a significantly lower potential, i.e between 5--15V lower. This means that in order to completely turn off a high-side P-FET we’ll have to drive it’s gate as high as it’s source, which is connected to the power supply. To turn the FET on, we have to lower the gate voltage by 5…15V below Vbat.
Because at the output of the uController we have not the necessary voltage to turn off the P-MOS we need an intermediate stage between the uController and the H-bridge. We call this intermediate stage level-shifter.
Here, the gate of the small-signal N-FET is driven by a suitable logic signal (and a logic level signal can easily open this N-FET) and the drain of it is pulled up to the gate-drive power supply, Vdrive. In our case to Vbat to turn off the P-MOS. When N-FET is driven by a logic '0' the output will be Vbat becasue it will be OFF. Else if the logic is '1' the N-FET will be open and the output will be 0V.
Summary: Q2 and Q3 transistors behave like an inversor and make posible to turn off the P-MOS high side increasing the voltage in the P-MOS gate.