Closed s-trinh closed 2 years ago
Thank you for bug report! The bug is caused by the trying of aligned reading of unaligned memory. The alignment checking of input array with alpha channel was missed for SSE4.1, AVX2 and AVX-512BW optimizations of function InterleaveBgra. The error was fixed.
Thanks :+1:
Hi,
We are experiencing some weird random segfault issue. Unfortunately, this is hard to reproduce.
See this post https://github.com/lagadic/visp/issues/1042 for a possible stacktrace. The input data is an array of
height=1
,width=32
, anduchar BGRA
data. Function call toSimdlib
isAvx2::InterleaveBgra()
.I was not able to get a correct stacktrace on my side, but you can find some additional logs here:
About the compiler flags: https://github.com/s-trinh/visp/blob/00709310e5b76b1d0a1011597fd33cdde4c2b1dc/3rdparty/simdlib/CMakeLists.txt
And we are not using aligned vectors.